1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a clock signal propagation gate. More particularly, the invention relates to techniques for reducing clock signal skew (or a time difference between clock signals arriving at respective end points) and for facilitating the delay adjustment of the clock signals.
2. Description of the Background Art
Design of a clock distribution circuit is important in synchronous pipeline design of LSI circuits. Techniques for the clock distribution circuit are mainly of two types: a single-buffer scheme and a clock-tree scheme. The clock-tree scheme can achieve reductions in power consumption and in area as compared with the single-buffer scheme, and also can easily control clock signals.
FIG. 5 is a circuit diagram of a typical clock distribution circuit of the clock-tree type. A clock signal inputted at a clock origin (or a starting point of a clock) is distributed through a buffer 200 to buffers 201 and 202. The clock signal passed through the buffer 201 is further distributed to buffers 203 and 204. Finally, these distributed clock signals reach sequential circuits (e.g., latches and flip-flops (FFs)) at the end points of the clock tree. Buffers 200 to 212 are shown in FIG. 5. Sequential circuits 213 to 216 each including a plurality of flip-flops operating on the rising edge of the clock signal are shown at the end points of the clock tree.
Various structures of the clock distribution circuit of the clock-tree type have been proposed. Recently, an H-tree scheme has been proposed which can provide a uniform layout of paths from the clock origin to the sequential circuits at the end points. The H-tree scheme is disclosed in xe2x80x9cA Clock Distribution Network for Microprocessors,xe2x80x9d 2000 Symposium on VLSI Circuits Digest of Technical Papers.
FIG. 6 is a circuit diagram of a clock distribution circuit of the clock-tree type capable of controlling the clock signal. The clock distribution circuit of FIG. 6 includes a control OR gate 224 and a control AND gate 226 in paths. These control gates 224 and 226 can stop feeding some or all of the clock signals to the sequential circuits at the end points. Buffers 220 to 223, 225, and 227 to 232 and sequential circuits 233 to 236 are shown in FIG. 6.
A path including the control AND gate 226 will be described. FIGS. 7A and 7B are partial circuit diagrams of the clock distribution circuit having the control AND gate. FIG. 7A shows a path from the clock origin to the sequential circuit 236 at one end point in the clock distribution circuit shown in FIG. 6. A clock signal inputted at the clock origin propagates through the buffers 220 and 222 to the control AND gate 226. The two-level control AND gate 226 includes an NAND gate 240 at the first level, and an inverter 245 at the second level.
FIG. 7B is a circuit diagram of the control AND gate 226. The NAND gate 240 at the first level includes pMOS transistors 241, 242 and nMOS transistors 243, 244. The inverter 245 at the second level includes a pMOS transistor 246 and an nMOS transistor 247.
The clock signal outputted from the control AND gate 226 propagates through buffers 228 and 232 to the sequential circuit 236 at the end point. The sequential circuit 236 shown in FIG. 7A is driven upon receipt of the rising edge of the clock signal.
The operation of the control AND gate 226 will be described. A control signal controls the propagation of the rising edge of the clock signal inputted to the control AND gate 226. When the control signal is LOW, the output from the control AND gate 226 remains LOW independently of the occurrence of a rising edge (or a LOW-to-HIGH signal transition) of the input clock signal. Thus, no rising edge of the clock signal propagates when the control signal for the control AND gate 226 is LOW.
On the other hand, when the control signal is HIGH, the input clock signal is inverted by the NAND gate 240 at the first level, and is then inverted again by the inverter 245 at the second level. Thus, the rising edge of the clock signal propagates when the control signal for the control AND gate 226 is HIGH.
Next, a path including the control OR gate 224 will be described. FIGS. 8A and 8B are partial circuit diagrams of the clock distribution circuit having the control OR gate. FIG. 8A shows a path from the clock origin to the sequential circuit 233 at one end point in the clock distribution circuit shown in FIG. 6. FIG. 8B is a circuit diagram of the two-level control OR gate 224 which includes a NOR gate 250 at the first level and an inverter 255 at the second level. The NOR gate 250 at the first level includes pMOS transistors 251, 252 and nMOS transistors 253, 254. The inverter 255 at the second level includes a pMOS transistor 256 and an nMOS transistor 257.
A control signal controls the propagation of the rising edge of the clock signal inputted to the control OR gate 224. When the control signal is LOW, the input clock signal is inverted by the NOR gate 250 at the first level, and is then inverted again by the inverter 255 at the second level. Thus, the rising edge of the clock signal propagates when the control signal for the control OR gate 224 is LOW.
On the other hand, when the control signal is HIGH, the output from the control OR gate 224 remains HIGH independently of the occurrence of a rising edge of the input clock signal. Thus, no rising edge of the clock signal propagates when the control signal for the control OR gate 224 is HIGH.
In the clock distribution circuits of the clock-tree type shown in FIGS. 5 and 6, differences exist in length of interconnect lines, in the number of adjacent interconnect lines and in the number of gate levels, depending upon the paths from the clock origin to the sequential circuits at the end points. This produces a delay difference between clock signals, depending on the interconnect line paths, to result in a tendency toward higher clock signal skew (or a greater time difference between clock signals arriving at respective end points). Further, when the sequential circuit at the end point is driven by the rising edge of the clock signal, there is a need for the clock distribution circuit to propagate the rising edge of the clock signal.
Each of the buffers in the clock distribution circuits shown in FIGS. 5 and 6 is a two-level buffer including two inverters 260 and 263, as shown in FIG. 9. The first-level inverter 260 includes a pMOS transistor 261 and an nMOS transistor 262, and the second-level inverter 263 includes a pMOS transistor 264 and an nMOS transistor 265. Since an interconnect line connected to the output of the buffer has a large parasitic capacitance, the pMOS transistor 264 for driving the interconnect line is designed to have a greater current-driving capability than that of the pMOS transistor 261, and the nMOS transistor 265 is designed to have a greater current-driving capability than that of the nMOS transistor 262. In general, the driving capability of the pMOS transistor 264 of the inverter 263 is less than that of the nMOS transistor 265 of the same inverter 263. Thus, if the rising edge of the clock signal is applied to the buffer shown in FIG. 9, the propagation delay of the clock signal increases after the clock signal passes through the buffer.
To solve the higher clock signal skew problem, it is necessary to increase the driving capability of the second-level inverter 263 or, particularly, the driving capability of the pMOS transistor 264. In other words, a solution to the problem is to increase the gate width of the pMOS transistor 264 of the second-level inverter 263. However, this solution increases the area of the pMOS transistor 264 to accordingly increase the area of the buffer itself. This results in the increase in the area of the clock distribution circuit to give rise to the problem of accordingly increasing power consumption of the clock distribution circuit.
Another solution is the use of a clock distribution circuit disclosed in xe2x80x9cP-boosted Source Followers: A Robust Energy-efficient Bus Driver Technique,xe2x80x9d 2001 Symposium on VLSI Circuits Digest of Technical Papers. However, this clock distribution circuit is constructed to involve the need for the addition of a new nMOS transistor to present a problem such that it is impossible to reduce the area of the clock distribution circuit. Further, a pMOS transistor in this clock distribution circuit also participates in the propagation of the rising edge of the clock signal.
The control AND gate 226 shown in FIGS. 7A and 7B has a drawback to be described below. When the control signal is HIGH and the rising edge of the clock signal is inputted to the control AND gate 226, the clock signal inputted to the NAND gate 240 at the first level makes a LOW-to-HIGH transition. The clock signal which is HIGH turns OFF the pMOS transistor 241 of the NAND gate 240 at the first level. The turning-OFF of the pMOS transistor 241 causes the nMOS transistors 243 and 244 to drive the inverter 245 at the second level. The buffer structure shown in FIG. 9 does not have the series-connected nMOS transistors 243 and 244. Thus, the control AND gate 226 cannot provide current characteristics and the like similar to those of the buffer shown in FIG. 9 in response to the rising edge of the clock signal.
The control OR gate 224 shown in FIGS. 8A and 8B has a drawback to be described below. When the control signal is LOW and the rising edge of the clock signal is inputted to the control OR gate 224, the clock signal inputted to the NOR gate 250 at the first level makes a LOW-to-HIGH transition. The clock signal which is HIGH turns OFF the pMOS transistor 252 of the NOR gate 250 at the first level. The turning-OFF of the pMOS transistor 252 causes the nMOS transistor 253 to drive the inverter 255 at the second level. Since the nMOS transistors 253 and 254 are connected in parallel and the nMOS transistor 254 is OFF, the control OR gate 224 becomes similar in construction to the buffer shown in FIG. 9. Thus, the control OR gate 224 can provide current characteristics and the like close to those of the buffer shown in FIG. 9 in response to the rising edge of the clock signal.
However, if the waveform of the input clock signal has a gentle slope, a short circuit current flows for a long time. Then, the influence of the pMOS transistors 251 and 252 becomes non-negligible, and the control OR gate 224 cannot provide the current characteristics and the like close to those of the buffer shown in FIG. 9 in response to the rising edge of the clock signal.
As described above, the clock distribution circuit which includes both the control AND gate 226 shown in FIGS. 7A and 7B and the control OR gate 224 shown in FIGS. 8A and 8B finds difficulties in adjusting the delay of the clock signal since the control AND gate 226 and the control OR gate 224 have different current characteristics and the like than those of the buffers. For this reason, the clock distribution circuit shown in FIG. 6 has clock signal skew higher than that of a clock distribution circuit comprised of only similar buffers.
It is an object of the present invention to provide a clock signal propagation gate capable of reducing clock signal skew, facilitating clock signal delay adjustment and controlling a clock signal, and a semiconductor integrated circuit including the clock signal propagation gate.
According to a first aspect of the present invention, a clock signal propagation gate includes an inverter, and a logic gate. The inverter includes: a first MOS transistor of a first conductivity type having a drain, a gate receiving a clock signal, and a source connected to a first potential point; and a second MOS transistor of a second conductivity type having a source connected to a second potential point, a drain connected to the drain of the first MOS transistor, and a gate connected to the gate of the first MOS transistor. The logic gate includes: a third MOS transistor of the second conductivity type having a gate connected directly to the drain of the first MOS transistor and to the drain of the second MOS transistor, a source connected to the second potential point, and a drain, the third MOS transistor having a current-driving capability greater than that of the first MOS transistor; a fourth MOS transistor of the first conductivity type having a gate, a drain connected to the drain of the third MOS transistor, and a source; a fifth MOS transistor of the first conductivity type having a drain connected to the source of the fourth MOS transistor, a source connected to the first potential point, and a gate; and a sixth MOS transistor of the second conductivity type having a drain connected to the drain of the third MOS transistor to serve as an output of the logic gate, a source connected to the second potential point, and a gate; The gate of one of the fourth and fifth MOS transistors is connected to the gate of the third MOS transistor. The gate of the other of the fourth and fifth MOS transistors is connected to the gate of the sixth MOS transistor. A transition of the clock signal from a first potential at the first potential point to a second potential at the second potential point propagates to the output of the logic gate when a logic corresponding to the second potential point is applied to the gate of the other of the fourth and fifth MOS transistors and to the gate of the sixth MOS transistor.
The clock signal propagation gate produces the effects of controlling the clock signal in a clock distribution circuit, providing current characteristics and the like close to those of a buffer, and reducing the influence of a short circuit current upon the slope of the waveform of the rising edge of the clock signal.
According to a second aspect of the present invention, a semiconductor integrated circuit includes a clock signal interconnect line, a buffer, at least one clock signal propagation gate, and a sequential circuit. The clock signal interconnect line propagates a rising edge of a clock signal. The buffer is on the clock signal interconnect line. The at least one clock signal propagation gate is the clock signal propagation gate as defined in the first aspect, and is on the clock signal interconnect line. The clock signal propagation gate propagates the clock signal when the first conductivity type is an n type, the second conductivity type is a p type, and a logic xe2x80x9chighxe2x80x9d is applied to the gates of the fourth and fifth MOS transistors. The sequential circuit is at an end point of the clock signal interconnect line. The sequential circuit is operated on the rising edge of the clock signal propagating through the clock signal interconnect line.
The semiconductor integrated circuit, which includes the clock signal propagation gate as defined in the first aspect, produces the effects of controlling the propagation of the rising edge of the clock signal in a clock distribution circuit, and providing clock signal skew as low as that of a clock distribution circuit comprised of only buffers.
According to a third aspect of the present invention, a semiconductor integrated circuit includes a clock signal interconnect line, a buffer, at least one clock signal propagation gate, and a sequential circuit. The clock signal interconnect line propagates a falling edge of a clock signal. The buffer is on the clock signal interconnect line. The at least one clock signal propagation gate is the clock signal propagation gate as defined in the first aspect, and is on the clock signal interconnect line. The clock signal. propagation gate propagates the clock signal when the first conductivity type is a p type, the second conductivity type is an n type, and a logic xe2x80x9clow xe2x80x9d is applied to the gates of the fourth and fifth MOS transistors. The sequential circuit is at an end point of the clock signal interconnect line. The sequential circuit is operated on the falling edge of the clock signal propagating through the clock signal interconnect line.
The semiconductor integrated circuit, which includes the clock signal propagation gate as defined in the first aspect, produces the effects of controlling the propagation of the falling edge of the clock signal in a clock distribution circuit, and providing clock signal skew as low as that of a clock distribution circuit comprised of only buffers.